Physically Aware Data Communication Optimization for Reconfigurable System Synthesis

Modern reconfigurable systems contain 100,000+ programmable logic elements. In order to program these devices, we must rely on system level design techniques to manage the complexity and increase the efficiency of the designer. In this paper, we present a physically aware system level design flow for mapping high level application specifications to programmable logic. In particular, we study the problem optimizing data communication of the variables in the application specification. The framework uses floorplan information to guide compiler optimizations. Our results show physically aware compiler transformations have the ability to reduce the wirelength by an average of 12%. However, compiler optimizations often modify the design which leads to an illegal floorplans. We develop a simple, yet effective, incremental floorplanner to handle the perturbations caused by compiler optimizations. We show that the proposed techniques can still reduce the wirelength of the final design by 6%, while maintaining a legal floorplan with the same area as the initial floorplan.